1. Field of the Invention
The present invention relates to a frequency multiplier for outputting a signal whose principal frequency is an even multiple of the frequency of an input signal.
2. Description of the Background Art
A frequency multiplier is used in a radio system and the like to convert an RF signal outputted from a VCO (voltage-controlled oscillator) into a frequency which is a multiple of, e.g. twice, the frequency of the RF signal. In a radio system employing the frequency multiplier, there is a significant difference between the frequency of an RF signal outputted from a power amplifier after the frequency conversion and the frequency of an RF signal outputted from the VCO. This system has the advantage of being able to avoid a VCO pulling problem such that the oscillation frequency of the VCO is varied by the RF signal amplified by the power amplifier, as compared with a system which does not performs the frequency conversion on the RF signal.
Recent advantages in miniaturization technology have improved the operating frequency of CMOS devices. This makes it possible to integrate the VCO and the frequency multiplier onto an RF transceiver chip, and a large number of wireless LSIs are disclosed and commercialized. In such wireless LSIs, circuit blocks are required to operate at lower voltages because the miniaturization of the CMOS devices involves the reduction in gate breakdown voltage. For example, a CMOS device with a line width of 0.18 μm is generally required to operate at a power supply voltage of 1.8 V, and RF circuits included in the CMOS device accordingly must operate at a voltage of not greater than 1.8 V.
A configuration known as a Gilbert-cell has conventionally been used in the frequency multiplier, as disclosed also in Japanese Patent Application Laid-Open No. 2003-229722. This configuration, in which three transistors including a transistor constituting a constant current circuit are connected in series, presents a problem such that a sufficient output amplitude cannot be ensured when the power supply voltage is 1.8 V.
A frequency multiplier capable of lower-voltage operation at a power supply voltage of not greater than 1.8 V is proposed in Kazuya Yamamoto et al., “1.2/2.4-GHz, 2.6/5.2-GHz-Band CMOS Frequency Doublers for Wireless Applications,” TECHNICAL REPORT OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, ED2003-210, pp. 25–30. The frequency multiplier disclosed in the article by Kazuya Yamamoto et al. uses two MOS transistors having respective sources connected to each other and respective drains connected to each other as a multiplier core capable of outputting a frequency component having a frequency which is an even multiple of an input signal. Thus, the number of transistors connected in series is one, and the lower-voltage operation at the power supply voltage of 1.8 V is achieved.
Techniques about the frequency multiplier are also disclosed in Japanese Patent Application Laid-Open No. 7-135424 (1995) and Japanese Patent Application Laid-Open No. 2003-283251.
In the technique disclosed in the article by Kazuya Yamamoto et al., the multiplier core has a differential input, and complementary signals outputted from a VCO or the like provided in its preceding stage are inputted to the differential input. Sometimes, the complementary signals are not completely complementary to each other, in which case in-phase components are contained in the input signals to the multiplier core to cause an output signal from the multiplier core to contain a fundamental component having the same frequency as the input signals. The fundamental component is sometimes contained in the power supply potential of the multiplier core because the input signals enter a power supply line and the like. In such a case, the fundamental component is also contained in the output signal from the multiplier core.
The technique disclosed in the article by Kazuya Yamamoto et al. converts the differential input into a single-phase output by means of the multiplier core, and then converts the single-phase output into a differential output by means of a differential amplifier. If an unwanted fundamental component is contained in the output signal from the multiplier core as described above, this background art technique cannot remove the unwanted fundamental component to result in the increase in the ratio (fundamental wave suppression ratio) of the fundamental component to a necessary signal component, e.g. a frequency component whose frequency is twice the frequency of the input signals. This creates a problem such that the fundamental component is not sufficiently suppressed.